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74VHC74 Dual D-Type Flip-Flop with Preset and Clear
October 1992 Revised February 2005
74VHC74 Dual D-Type Flip-Flop with Preset and Clear
General Description
The VHC74 is an advanced high speed CMOS Dual DType Flip-Flop fabricated with silicon gate CMOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The signal level applied to the D input is transferred to the Q output during the positive going transition of the CK pulse. CLR and PR are independent of the CK and are accomplished by setting the appropriate input LOW. An input protection circuit ensures that 0V to 7V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5V to 3V systems and two supply systems such as battery backup. This circuit prevents device destruction due to mismatched supply and input voltages.
Features
s High Speed: fMAX
170 MHz (typ) at TA VNIL
25qC
s High noise immunity: VNIH s Low power dissipation: ICC
28% VCC (min) 25qC
s Power down protection is provided on all inputs
2 PA (max) at TA
s Pin and function compatible with 74HC74
Ordering Code:
Order Number 74VHC74M 74VHC74MX_NL 74VHC74SJ 74VHC74MTC 74VHC74MTCX_NL (Note 1) 74VHC74N Package Number M14A M14A M14D MTC14 MTC14 N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter "X" to the ordering code. Pb-Free package per JEDED J-STD-020B. Note 1: "_NL" indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
(c) 2005 Fairchild Semiconductor Corporation
DS011505
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74VHC74
Logic Symbol
IEEE/IEC
Connection Diagram
Pin Descriptions
Pin Names D1 , D2 CK1, CK2 CLR1, CLR2 PR1, PR2 Q1, Q1, Q2, Q2 Description Data Inputs Clock Pulse Inputs Direct Clear Inputs Direct Preset Inputs Output
Truth Table
Inputs CLR L H L H H H PR H L L H H H D X X X L H X CK X X Q L H L H Qn Outputs Q H L H L Qn No Change Clear Preset Function
Note 2: This configuration is nonstable; that is, it will not persist when preset and clear inputs return to their inactive (HIGH) state.

X
H (Note 2) H (Note 2)
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2
74VHC74
Absolute Maximum Ratings(Note 3)
Supply Voltage (VCC ) DC Input Voltage (VIN) DC Output Voltage (VOUT) Input Diode Current (IIK) Output Diode Current (IOK) DC Output Current (IOUT) DC VCC /GND Current (ICC ) Storage Temperature (TSTG) Lead Temperature (TL) Soldering (10 seconds) 260qC
0.5V to 7.0V 0.5V to 7.0V 0.5V to VCC 0.5V 20 mA r20 mA r25 mA r50 mA 65qC to 150qC
Recommended Operating Conditions (Note 4)
Supply Voltage (VCC) Input Voltage (VIN) Output Voltage (VOUT) Operating Temperature (TOPR) Input Rise and Fall Time (tr, tf) VCC VCC 3.3V r 0.3V 5.0V r 0.5V 0 a 100 ns/V 0 a 20 ns/V 2.0V to 5.5V 0V to 5.5V 0V to VCC
40qC to 85qC
Note 3: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading varaibles. Fairchild does not recommend operation outside databook specifications. Note 4: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol VIH VIL VOH Parameter HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage VCC (V) 2.0 3.0 5.5 2.0 3.0 5.5 2.0 3.0 4.5 3.0 4.5 VOL LOW Level Output Voltage 2.0 3.0 4.5 3.0 4.5 IIN ICC Input Leakage Current Quiescent Supply Current 0 5.5 5.5 1.9 2.9 4.4 2.58 3.94 0.0 0.0 0.0 0.1 0.1 0.1 0.36 0.36 2.0 3.0 4.5 TA Min 1.50 0.7 VCC 0.50 0.3 VCC 1.9 2.9 4.4 2.48 3.80 0.1 0.1 0.1 0.44 0.44 V IOL IOL VIN VIN 4 mA 8 mA V V VIN IOH IOH VIH IOL or VIL V 25qC Typ Max TA
40qC to 85qC
Max
Min 1.50 0.7 VCC
Units V
Conditions
0.50 0.3 VCC
V VIN VIH IOH or VIL
50 PA
4 mA 8 mA
50 PA
r0.1
2.0
r1.0
20.0
PA PA
5.5V or GND VCC or GND
3
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74VHC74
AC Electrical Characteristics
Symbol fMAX Parameter Maximum Clock Frequency 5.0 r 0.5 tPLH tPHL Propagation Delay Time (CK-Q, Q) 5.0 r 0.5 tPLH tPHL Propagation Delay Time (CLR, PR -Q, Q) 5.0 r 0.5 CIN CPD Input Capacitance Power Dissipation Capacitance
Note 5: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained from the equation: ICC (opr.) CPD * VCC * fIN I CC/2 (per F/F).
VCC (V) 3.3 r 0.3
TA Min 80 50 130 90
25qC Typ 125 75 170 115 6.7 9.2 4.6 6.1 7.6 10.1 4.8 6.3 4 25 11.9 15.4 7.3 9.3 12.3 15.8 7.7 9.7 10 Max
TA
40qC to 85qC
Max 70 45
Min
Units MHz MHz CL CL CL CL CL CL CL CL CL CL CL CL
Conditions 15 pF 50 pF 15 pF 50 pF 15 pF 50 pF 15 pF 50 pF 15 pF 50 pF 15 pF 50 pF Open
110 75 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 14.0 17.5 8.5 10.5 14.5 18.0 9.0 11.0 10
3.3 r 0.3
ns ns ns ns pF pF
3.3 r 0.3
VCC
(Note 5)
AC Operating Requirements
Symbol tW(L) tW(H) tW(L) tS tH Minimum Pulse Width (CLR, PR) Minimum Setup Time Minimum Hold Time Parameter Minimum Pulse Width (CK) VCC (V) (Note 6) 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 tREC Minimum Recovery Time (CLR, PR) 3.3 5.0
Note 6: VCC is 3.3 r 0.3V or 5.0 r 0.5V
TA Typ
25qC
TA
40qC to 85qC
Units
Guaranteed Minimum 6.0 5.0 6.0 5.0 6.0 5.0 0.5 0.5 5.0 3.0 7.0 5.0 7.0 5.0 7.0 5.0 0.5 0.5 5.0 3.0
ns
ns ns ns
ns
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74VHC74
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M14A
5
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74VHC74
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D
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6
74VHC74
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC14
7
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74VHC74 Dual D-Type Flip-Flop with Preset and Clear
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N14A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 8 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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